The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Jul. 03, 2007
Filed:
Jan. 14, 2003
Toshiki Matsukawa, Fukui, JP;
Yasuharu Kinoshita, Fukui, JP;
Shoji Hoshitoku, Osaka, JP;
Masaharu Takahashi, Osaka, JP;
Yoshinori Ando, Osaka, JP;
Toshiki Matsukawa, Fukui, JP;
Yasuharu Kinoshita, Fukui, JP;
Shoji Hoshitoku, Osaka, JP;
Masaharu Takahashi, Osaka, JP;
Yoshinori Ando, Osaka, JP;
Matsushita Electric Industrial Co., Ltd., Osaka, JP;
Abstract
A multiple chip resistor is manufactured in the following method. First electrode layers are formed on a first surface of a substrate. Resistor elements electrically connected to the first electrode layers, respectively, are formed on the first surface of the substrate. Slits are formed in the substrate for separating the first electrode layers. Edge electrodes connected to the first electrode layers at the edges of the slits, respectively, are formed on respective edges at the slits of the substrate. The substrate is divided at the slits into strip substrates. Portions of the edge electrodes are removed for electrically isolating the resistor elements from each other. The method provides the edge electrodes on each strip substrate with an improved dimensional accuracy, hence allowing the edge electrodes to be isolated electrically from each other. Consequently, the multiple chip resistor is prevented from being mounted defectively when the resistor is surface-mounted.