The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Patent No.:

US 7237220 B1

PDF
Full Text
Expired
Date of Patent:
Jun. 26, 2007

Filed:

Jun. 23, 2005
Applicants:

Osamu Ogawa, Neyagawa, JP;

Dai Hattori, Otsu, JP;

Keiichi Kurokawa, Takaraduka, JP;

Masahiko Toyonaga, Kochi, JP;

Inventors:

Osamu Ogawa, Neyagawa, JP;

Dai Hattori, Otsu, JP;

Keiichi Kurokawa, Takaraduka, JP;

Masahiko Toyonaga, Kochi, JP;

Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
G06F 17/50 (2006.01);
U.S. Cl.
CPC ...
Abstract

A CDFG which is a graph representing calculations and a data flow included in the design specifications of a circuit is generated Sa clock cycle required for the processing is obtained and thus an allocated resource connection graph is generated SWhen the allocated resource connection graph includes nodes to which hardware resources having the same function are allocated, a sharing edge for controlling sharing of the nodes is added between the nodes SA provisional layout of the allocated resource connection graph having the sharing edge added thereto is provided Sand the nodes of the allocated resource connection graph are shared based on the layout result SThe sharing edge is provided with attribute or weight such as attraction or repulsion. Thus, the distance between the nodes in the layout result is controlled and the degree at which the resources are shared is controlled.


Find Patent Forward Citations

Ogawa, Osamu. (2007). High level synthesis method for semiconductor integrated circuit (U.S. Patent No. 7237220). U.S. Patent and Trademark Office. https://idiyas.com/patent/badge/7237220

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