The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jun. 26, 2007

Filed:

May. 24, 2005
Applicants:

Thang M. Tran, Austin, TX (US);

Raul A. Garibay, Jr., Austin, TX (US);

Muralidharan S. Chinnakonda, Austin, TX (US);

Paul K. Miller, Dripping Springs, TX (US);

Inventors:

Thang M. Tran, Austin, TX (US);

Raul A. Garibay, Jr., Austin, TX (US);

Muralidharan S. Chinnakonda, Austin, TX (US);

Paul K. Miller, Dripping Springs, TX (US);

Assignee:
Attorneys:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
G06F 12/00 (2006.01);
U.S. Cl.
CPC ...
Abstract

A processor comprises decode logic that determines an instruction type for each instruction fetched, a first level cache, a second level cache coupled to the first level cache, and control logic operatively coupled to the first and second level caches. The control logic preferably causes cache linefills to be performed to the first level cache upon cache misses for a first type of instruction, but precludes linefills from being performed to the first level cache for a second type of instruction.


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