The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jun. 26, 2007

Filed:

Mar. 29, 2006
Applicants:

Lorenzo Bedarida, Vinercate, IT;

Danut Manea, Cupertino, CA (US);

Mirella Marsella, Milan, IT;

Andrea Sacco, Alessandria, IT;

Inventors:

Lorenzo Bedarida, Vinercate, IT;

Danut Manea, Cupertino, CA (US);

Mirella Marsella, Milan, IT;

Andrea Sacco, Alessandria, IT;

Assignee:

Atmel Corporation, San Jose, CA (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G05F 1/10 (2006.01);
U.S. Cl.
CPC ...
Abstract

A current mirror comprising: a current source; a first p-channel MOS transistor having a source coupled to an operating potential, and a gate and a drain coupled to the current source; a second p-channel MOS transistor having a source coupled to the operating potential, a gate coupled to the gate of the first p-channel transistor, and a drain; a first n-channel MOS transistor having a source coupled to ground, and a gate and a drain coupled to the drain of the second p-channel transistor; a zero-threshold n-channel MOS transistor having a drain coupled to a current-output node, a gate coupled to the gate of the first n-channel transistor, and a source; and a second n-channel MOS transistor having a source coupled to ground, and a gate coupled to the gate of the first n-channel transistor and a drain coupled to the source of the zero-threshold n-channel transistor.


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