The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Jun. 26, 2007
Filed:
Oct. 01, 2004
Axel Brintzinger, Dresden, DE;
Octavio Trovarelli, Dresden, DE;
David Wallis, Dresden, DE;
Wolfgang Leiberg, Dresden, DE;
Axel Brintzinger, Dresden, DE;
Octavio Trovarelli, Dresden, DE;
David Wallis, Dresden, DE;
Wolfgang Leiberg, Dresden, DE;
Infineon Technologies AG, Munich, DE;
Abstract
An arrangement for protecting fuses/anti-fuses on chips which serve to activate redundant circuits or chip functions includes a passivation layer (e.g., hard passivation) arranged on a fully processed chip with the exception of metal contacts of a metallization level and the fuses. The chip is provided with a redistribution layer that is electrically contact-connected to the metallization level, and to a process for protecting such fuses/anti-fuses. The invention is now based on the object of ensuring sufficient protection of fuses/anti-fuses on integrated circuits. This is achieved by virtue of the fact that a dielectric (), which covers at least the region of the fuses/anti-fuses () and to which the redistribution layer () comprising the combination of materials Cu/Ni/Au is applied, is arranged on the passivation layer ().