The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jun. 19, 2007

Filed:

Oct. 06, 2004
Applicants:

Donald Audley Staab, Sunnyvale, CA (US);

Ian L. Mcewen, Golden, CO (US);

Reto Stamm, Sunnyvale, CA (US);

Phoumra Tan, San Jose, CA (US);

Inventors:

Donald Audley Staab, Sunnyvale, CA (US);

Ian L. McEwen, Golden, CO (US);

Reto Stamm, Sunnyvale, CA (US);

Phoumra Tan, San Jose, CA (US);

Assignee:

Xilinx, Inc., San Jose, CA (US);

Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
G06F 17/50 (2006.01);
U.S. Cl.
CPC ...
Abstract

Identification of a faulty net in a design implemented on a programmable logic device (PLD). In one approach, configuration data is generated to implement a duplicate circuit of a failing sub-circuit in the design. The PLD is configured with the configuration data that implements the failing sub-circuit and the duplicate circuit, and at least one set of input signals is applied to the sub-circuit and the duplicate circuit. A signal from each net in the sub-circuit is compared on the PLD to a corresponding net in the duplicate circuit. In response to the signal from the net in the sub-circuit being unequal to a signal from the corresponding net in the duplicate circuit, the net in the sub-circuit is identified as faulty.


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