The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Jun. 19, 2007
Filed:
Sep. 30, 2003
Dharma R. Konda, Aliso Viejo, CA (US);
Kathy K. Caballero, Huntingdon Beach, CA (US);
Sanjaya Anand, Coto de Caza, CA (US);
Ashish Bhargava, Irvine, CA (US);
Rajendra R. Gandhi, Laguna Niguel, CA (US);
Kuangfu David Chu, Irvine, CA (US);
Cam Le, Irvine, CA (US);
Dharma R. Konda, Aliso Viejo, CA (US);
Kathy K. Caballero, Huntingdon Beach, CA (US);
Sanjaya Anand, Coto de Caza, CA (US);
Ashish Bhargava, Irvine, CA (US);
Rajendra R. Gandhi, Laguna Niguel, CA (US);
Kuangfu David Chu, Irvine, CA (US);
Cam Le, Irvine, CA (US);
QLOGIC, Corporation, Aliso Viejo, CA (US);
Abstract
A method and system for performing data integrity process is provided. The method includes selecting a cyclic redundancy code ('CRC') mode from amongst append, validate and keep, and validate and remove mode. If the append mode is selected, then CRC is appended after each data block boundary. A CRC seed value is incremented for each data block providing a unique CRC value for each data block. If validate and keep mode is selected, then CRC accompanying any data is compared to CRC that may have been accumulated. If validate and remove mode is selected, then CRC is first validated and then CRC is removed before data is sent out. The system includes CRC logic that allows firmware running on an adapter to select one of plural CRC modes including append, validate and keep, and validate and remove mode.