The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Jun. 19, 2007
Filed:
Oct. 09, 2003
Xiao Hong Du, Colorado Springs, CO (US);
Jarrod Eliason, Colorado Springs, CO (US);
Yunchen Qiu, Plano, TX (US);
Bill Kraus, Palmer Lake, CO (US);
Xiao Hong Du, Colorado Springs, CO (US);
Jarrod Eliason, Colorado Springs, CO (US);
Yunchen Qiu, Plano, TX (US);
Bill Kraus, Palmer Lake, CO (US);
Texas Instruments Incorporated, Dallas, TX (US);
Abstract
This invention is a new CMOS voltage booster () having an output which can be used in memories to boost the word line voltage above VDD or other voltage boosting applications. The CMOS booster includes a NMOS FET (MN) to charge a boosting capacitor (C) to VDD at the end of each memory access and includes a PMOS FET (MP, MP) to keep the voltage at the output at VDD during standby. By using this combination, the word line rise time, the size of the booster, and the power consumption during access are significantly reduced. The gate of the NMOS FET (MN) is boosted above VDD+Vthn by a small capacitor (C) to charge the word line boosting capacitor to VDD at the end of each memory access. The small capacitor (C) is pre-charged to VDD by a NMOSFET (MN) whose gate is connected to the word line boosting capacitor. The gate of each PMOS FET (MP, MP) is shorted to its source to turn if off during boostenig. Transistor (MP) facilitates boosting the NMOS FET (MN) above VDD.