Output stage interface circuit for outputting digital data onto a data bus

Abstract

An output stage interface circuit () comprises a main bipolar transistor (Q) coupling a data output terminal () to a first rail () to which the positive of the power supply voltage (V) is applied, and a substrate diffusion isolated main NMOS transistor (MN) coupling the data output terminal () to a second rail () which is held at ground. Control signals from a data control circuit () selectively operate the main bipolar transistor (Q) and the main MOS transistor (MN) for determining the logic high and low states of the data output terminal () during data output. A back gate () of the main MOS transistor (MN) is independently configurable, and is selectively and alternately coupleable to one of the second rail () and the data output terminal () in response to the voltage on the data output terminal (), so that when the voltage on the data output terminal () is pulled below a voltage reference (V), the back gate () is coupled to the data output terminal () for preventing a parasitic bipolar transistor (Q) and a parasitic diode (D) of the main MOS transistor (MN) sourcing current to the data bus. First and second primary buffer circuits () and () are coupled between the first rail () and the back gate () of the main MOS transistor (MN), so that when the voltage on the data output terminal () is pulled below the voltage reference (V), the base () and the gate () of the main bipolar transistor (Q) and the main MOS transistor (MN) can be pulled to the voltage on the data output terminal () for maintaining the main bipolar transistor (Q) and the main MOS transistor (MN) in the off-state.