Power-on solution to avoid crowbar current for multiple power supplies' inputs/outputs

Abstract

Techniques to avoid crowbar current are provided. An integrated circuit according to an embodiment of the present invention includes a first node having a first supply voltage level. A first level shift circuit is connected between the first node and a first path. A second level shift circuit is connected between the first node and a second path. The first path includes an even number of inverter stages, while the second path includes an odd number of inverter stages. The first and second level shift circuits are configured to output a signal at the second supply voltage level. The integrated circuit also includes a PMOS transistor and an NMOS transistor connected in series between a second node having the second supply voltage level and a reference voltage. A gate of the PMOS transistor is connected to the first path, and a gate of the NMOS transistor connected to the second path. An I/O pad connected between the PMOS and NMOS transistors has high impedance during a power-on period when the second node is powered up before the first node. In other specific embodiments, the inverter stages of the first path and the second path can be replaced with pull-up or pull-down circuits, respectively.