The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jun. 19, 2007

Filed:

Nov. 04, 2004
Applicants:

Kiyoyuki Morita, Joetsu, JP;

Noboru Yamada, Hirakata, JP;

Akihito Miyamoto, Hirakata, JP;

Takashi Ohtsuka, Toyonaka, JP;

Hideyuki Tanaka, Hirakata, JP;

Inventors:

Kiyoyuki Morita, Joetsu, JP;

Noboru Yamada, Hirakata, JP;

Akihito Miyamoto, Hirakata, JP;

Takashi Ohtsuka, Toyonaka, JP;

Hideyuki Tanaka, Hirakata, JP;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 21/06 (2006.01);
U.S. Cl.
CPC ...
Abstract

A non-volatile memory comprising: a first substrate () and a second substrate (), the first substrate () having a plurality of switching elements () arranged in matrix, and a plurality of first electrodes () connected to the switching element (), the second substrate () having a conductive film (), and a recording layer () whose resistance value changes by application of an electric pulse, wherein the plurality of first electrodes () are integrally covered by the recording layer (), the recording layer () thereby being held between the plurality of first electrodes () and the conductive film (); the first substrate () further comprising a second electrode (), the second electrode () being electrically connected to the conductive film (), the voltage of which is maintained at a set level while applying current to the recording layer (). This non-volatile memory achieves high integration at low cost.


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