The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Jun. 19, 2007
Filed:
Mar. 04, 2005
Applicants:
James Guenter, Garland, TX (US);
Robert Hawthorne, Garland, TX (US);
Jose Aizpuru, Murphy, TX (US);
Inventors:
Assignee:
Finisar Corporation, Sunnyvale, CA (US);
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 21/00 (2006.01);
U.S. Cl.
CPC ...
Abstract
A photo-imaged stress management layer for a semiconductor device is described. The stress management layer is located on an outer surface of a semiconductor device and may be patterned to address certain stress compensation requirements of the semiconductor device. The stress management layer may be manufactured onto the semiconductor device using a photolithographic procedure that allows both simple and complex patterns to be realized.
Guenter, James. (2007). Photo-imaged stress management layer for semiconductor devices (U.S. Patent No. 7232692). U.S. Patent and Trademark Office. https://idiyas.com/patent/badge/7232692
Data source: USPTO (United States Patent and Trademark Office) public patent records. Weekly synchronization. How IDiyas builds this profile