The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jun. 12, 2007

Filed:

Apr. 30, 2004
Applicants:

Nigel G. Herron, San Jose, CA (US);

Ahmad R. Ansari, San Jose, CA (US);

Stephen M. Douglass, Saratoga, CA (US);

Anthony Correale, Jr., Raleigh, NC (US);

Leslie M. Debruyne, Cary, NC (US);

Inventors:

Nigel G. Herron, San Jose, CA (US);

Ahmad R. Ansari, San Jose, CA (US);

Stephen M. Douglass, Saratoga, CA (US);

Anthony Correale, Jr., Raleigh, NC (US);

Leslie M. DeBruyne, Cary, NC (US);

Assignees:

Xilinx, Inc., San Jose, CA (US);

International Business Machines, Armonk, NY (US);

Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
G06F 9/45 (2006.01); G01R 31/28 (2006.01);
U.S. Cl.
CPC ...
Abstract

Method and apparatus for generating a test program for a programmable logic device having an embedded processor. Predetermined code is obtained to exercise at least one speed limiting path identified. To the predetermined code is added wrapper code to provide the test program, the wrapper code in part for loading the predetermined code into cache of the embedded processor for testing the at least one speed limiting path of the embedded processor identified.


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