The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jun. 12, 2007

Filed:

Sep. 02, 2005
Applicants:

Chen-chi Huang, Yuan Kang, TW;

Tsan-lin Chen, Hsinchu Hsien, TW;

Shang-pin Huang, Hsinchu Hsien, TW;

Chih-yuan Wu, Hsinchu, TW;

Inventors:

Chen-Chi Huang, Yuan Kang, TW;

Tsan-Lin Chen, Hsinchu Hsien, TW;

Shang-Pin Huang, Hsinchu Hsien, TW;

Chih-Yuan Wu, Hsinchu, TW;

Assignee:
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G11C 7/00 (2006.01);
U.S. Cl.
CPC ...
Abstract

A high access rate flash control provided for accessing more than one flash memory chip having different access timing specifications is disclosed. The controller comprises a read/write(R/W) pulse generator, a R/W delay chain circuit, a sampling delay chain circuit, a bi-directional feedback pad (PAD), a data bus sampler, and a second pad (PAD). In an embodiment, the flash controller using a fix clock to generate synchronized Read/Write pulse which is then appropriated adjusted by the R/W delay chain circuit to provide optimum R/W control signal. The adjusted R/W signal is than outputted by a bi-directional pad to flash memory chips. With the external signal feedback function, the bi-directional pad has associated with the sampling delay chain, the time latency due to pads can be eliminated nearly. Thus, the flash controller can approach high rate to access flash chips.


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