The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Jun. 12, 2007
Filed:
Mar. 27, 2006
Qin Huang, Cary, NC (US);
Abdel-aty Edris, Sunnyvale, CA (US);
Michael R. Ingram, Harrison, TN (US);
Siriroj Sirisukprasert, Bangkok, TH;
Qin Huang, Cary, NC (US);
Abdel-Aty Edris, Sunnyvale, CA (US);
Michael R. Ingram, Harrison, TN (US);
Siriroj Sirisukprasert, Bangkok, TH;
North Carolina State University, Raleigh, NC (US);
Tennessee Valley Authority, Knoxville, TN (US);
Electrical Power Research Institute, Inc., Palo Alto, CA (US);
Abstract
A method of balancing the voltage of DC links in a cascaded multi-level converter (CMC) semiconductor circuit, including the steps of providing a plurality of H-bridge converters per phase in the CMC circuit and utilizing a three phase duty cycle value from the main controller to determine a normalized duty cycle value, a ceiling duty cycle value and a floor duty cycle value. The normalized duty cycle value and an output current of the CMC is used to determine the direction and polarity of a capacitor current, and utilizing the capacitor current to determine a plurality of output capacitor voltages. A voltage summation result and direction is obtained from a ceiling index pointer and a floor index pointer and the voltage summation result, direction from the ceiling index pointer and a floor index pointer are used to create a combined switching table for the H-bridge converters. A pulse width modulator is utilized to balance the voltage of the DC links and thereby eliminate DC-capacitor voltage imbalance.