The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jun. 12, 2007

Filed:

Mar. 22, 2005
Applicants:

Setsuo Noguchi, Yokohama, JP;

Kohtaroh Takahashi, Yokohama, JP;

Eiji Matsunaga, Yokohama, JP;

Yoshihiko Saiki, Sendai, JP;

Satoshi Arai, Sendai, JP;

Sadamu Toita, Sendai, JP;

Inventors:

Setsuo Noguchi, Yokohama, JP;

Kohtaroh Takahashi, Yokohama, JP;

Eiji Matsunaga, Yokohama, JP;

Yoshihiko Saiki, Sendai, JP;

Satoshi Arai, Sendai, JP;

Sadamu Toita, Sendai, JP;

Assignees:

NEC Tokin Corporation, Miyagi, JP;

Airex Inc., Yokohama, Kanagawa, JP;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01G 9/04 (2006.01); H01G 9/145 (2006.01);
U.S. Cl.
CPC ...
Abstract

A printed circuit board which is thin and incorporates a large-capacitance capacitor function and a manufacturing method thereof. In one embodiment, the printed circuit board manufacturing method includes forming inner layer conductor circuits on a core substrate; forming a recess part on the core substrate; housing, in a recess part, a planar capacitor device that is not resin molded and has electrodes on the surfaces on a shared side; interposing the same between insulator resin and conductor metal foil to heat pressurize the same for forming a multi-layer plate; forming via holes for electrically connecting an outer layer conductor circuit to the electrodes of the capacitor device; forming a conductor layer on them; and forming the outer layer conductor circuits on the surfaces of the multi-layer plate.


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