The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jun. 12, 2007

Filed:

Oct. 15, 2004
Applicant:

Yoshihiro Ohara, Kanagawa, JP;

Inventor:

Yoshihiro Ohara, Kanagawa, JP;

Assignee:

NEC Electronics Corporation, Kawasaki-shi, Kanagawa, JP;

Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
H03K 19/00 (2006.01); G01R 31/28 (2006.01);
U.S. Cl.
CPC ...
Abstract

In a semiconductor logic circuit device including an internal circuit, a group of first pads, a group of second pads, and a plurality of input buffers, each connected between the internal circuit and one of the first and second pads, for supplying input signals from their corresponding pads to the internal circuit, each of the first pads is connected to at least one of a pull-up circuit for pulling up a voltage at each of the first pads to a first voltage, and a pull-down circuit for pulling down the voltage at each of the first pads to a second voltage lower than the first voltage.


Find Patent Forward Citations

Ohara, Yoshihiro. (2007). Semiconductor logic circuit device having pull-up/pull-down circuit for input buffer pad and wafer-probing testing method therefor (U.S. Patent No. 7230446). U.S. Patent and Trademark Office. https://idiyas.com/patent/badge/7230446

Data source: USPTO (United States Patent and Trademark Office) public patent records. Weekly synchronization. How IDiyas builds this profile

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