The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jun. 12, 2007

Filed:

Aug. 31, 2005
Applicants:

Franz Dietz, Untereisesheim, DE;

Volker Dudek, Brackenheim, DE;

Michael Graf, Leutenbach, DE;

Stefan Schwantes, Heilbronn, DE;

Gayle W. Miller, Jr., Colorado Springs, CA (US);

Inventors:

Franz Dietz, Untereisesheim, DE;

Volker Dudek, Brackenheim, DE;

Michael Graf, Leutenbach, DE;

Stefan Schwantes, Heilbronn, DE;

Gayle W. Miller, Jr., Colorado Springs, CA (US);

Assignee:

Atmel Corporation, San Jose, CA (US);

Attorneys:
Primary Examiner:
Int. Cl.
CPC ...
H01L 23/544 (2006.01);
U.S. Cl.
CPC ...
Abstract

A first mark, in a double-well integrated circuit technology, is formed by a first etching of a first mask layer on top of an ONO stack. After a first well is doped, a second etching occurs at the first etching sites in the uppermost layer of oxide of the ONO stack forming a first alignment artifact. A second mask layer is applied after removing the first mask layer. A second well doping occurs at second mask layer etching sites to maintain clearance between the two wells within active areas and provide an overlap of the two wells in a frame area. At the first alignment artifact in the overlap of the two wells, further etchings remove remaining layers of the ONO stack and remove silicon from the upper most layer of the semiconductor forming a second registration mark, which may be covered by a protective layer.


Find Patent Forward Citations

Loading…