The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jun. 12, 2007

Filed:

Jun. 28, 2004
Applicant:

Hyung-hwan Kim, Ichon, KR;

Inventor:

Hyung-Hwan Kim, Ichon, KR;

Assignee:

Hynix Semiconductor Inc., Kyoungki-do, KR;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 21/3205 (2006.01); H01L 21/4763 (2006.01); H01L 21/20 (2006.01); H01L 21/336 (2006.01); H01L 21/8242 (2006.01);
U.S. Cl.
CPC ...
Abstract

Disclosed is a method for forming landing plug contacts in a semiconductor device. The method includes the steps of: forming a plurality of gate structures on a substrate, each gate structure including a gate hard mask; forming an inter-layer insulation layer on the gate structures; planarizing the inter-layer insulation layer through a chemical mechanical polishing (CMP) process until the gate hard mask is exposed; forming a hard mask material on the planarized inter-layer insulation layer; patterning the hard mask material, thereby forming a hard mask; forming a plurality of contact holes exposing the substrate disposed between the gate structures by etching the planarized inter-layer insulation layer with use of the hard mask as an etch mask; forming a polysilicon layer on the contact holes; and forming the landing plug contacts buried into the contact holes through a planarization process performed to the polysilicon layer until the gate hard mask is exposed.


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