The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Jun. 12, 2007
Filed:
Jan. 29, 2002
Jean-ho Song, Pyeongtaek, KR;
Joon-hoo Choi, Seoul, KR;
Beom-rak Choi, Seoul, KR;
Myung-koo Kang, Seoul, KR;
Sook-young Kang, Seoul, KR;
Jean-Ho Song, Pyeongtaek, KR;
Joon-Hoo Choi, Seoul, KR;
Beom-Rak Choi, Seoul, KR;
Myung-Koo Kang, Seoul, KR;
Sook-Young Kang, Seoul, KR;
Abstract
A manufacturing method of a thin film transistor. An amorphous silicon thin film is formed on an insulating substrate, and is crystallized by a lateral solidification process with illumination of laser beams into the amorphous silicon thin film to form a polysilicon thin film. Next, protrusion portions protruding from the surface of the polysilicon thin film are removed by plasma dry-etching using a gas mixture including Cl, SFand Ar at the ratio of 3:1:2 to smooth the surface of the polysilicon thin film, and the semiconductor layer is formed by patterning the polysilicon thin film. A gate insulating film covering the semiconductor layer is formed and a gate electrode is formed on the gate insulating film opposite the semiconductor layer. A source region and a drain region opposite each other with respect to the gate electrode are formed by implanting impurities into the semiconductor layer and a source electrode and drain electrode are formed to be electrically connected to the source region and drain region.