The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jun. 05, 2007

Filed:

Jan. 30, 2004
Applicants:

Eric R. Keller, Boulder, CO (US);

Gordon J. Brebner, Monte Sereno, CA (US);

Philip B. James-roxby, Longmont, CO (US);

Chidamber R. Kulkarni, San Jose, CA (US);

Inventors:

Eric R. Keller, Boulder, CO (US);

Gordon J. Brebner, Monte Sereno, CA (US);

Philip B. James-Roxby, Longmont, CO (US);

Chidamber R. Kulkarni, San Jose, CA (US);

Assignee:

Xilinx, Inc., San Jose, CA (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G06F 17/50 (2006.01);
U.S. Cl.
CPC ...
Abstract

Programmable architecture for implementing a message processing system using an integrated circuit is described. In an example, first attributes are defined for a plurality of threads within the integrated circuit. Second attributes are defined for a memory associated with the integrated circuit. Third attributes are defined for an interconnection topology associated with at least one of the memory and the plurality of threads. Fourth attributes are defined for an interface to at least one of the memory and the plurality of threads.


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