The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jun. 05, 2007

Filed:

Nov. 30, 2004
Applicants:

Cheng-wen Wu, Hsinchu, TW;

Rei-fu Huang, Sinhua Township, Tainan County, TW;

Chin-lung Su, Taipei, TW;

Wen-ching Wu, Jhudong Township, Hsinchu County, TW;

Yeong-jar Chang, Taiping, TW;

Kun-lun Luo, Hsinchu, TW;

Shen-tien Lin, Houli Township, Taichung County, TW;

Inventors:

Cheng-Wen Wu, Hsinchu, TW;

Rei-Fu Huang, Sinhua Township, Tainan County, TW;

Chin-Lung Su, Taipei, TW;

Wen-Ching Wu, Jhudong Township, Hsinchu County, TW;

Yeong-Jar Chang, Taiping, TW;

Kun-Lun Luo, Hsinchu, TW;

Shen-Tien Lin, Houli Township, Taichung County, TW;

Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
G11C 29/00 (2006.01);
U.S. Cl.
CPC ...
Abstract

The present invention provides a method and apparatus for a memory build-in self-diagnosis and repair with syndrome identification. It uses a fail-pattern identification and a syndrome-format structure to identify faulty rows, faulty columns and single faulty word in the memory during the testing process, then exports the syndrome information. Based on the syndrome information, a redundancy analysis algorithm is applied to allocate the spare memory elements repairing the faulty memory cells. It has a sequencer with enhanced fault syndrome identification, a build-in redundancy-analysis circuit with improved redundancy utilization, and an address reconfigurable circuit with reduced timing penalty during normal access. The invention reduces the occupation time and the required capture memory space in the automatic test equipment. It also increases the repair rate and reduces the required area overhead.


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