Measuring pulse edge delay value relative to a clock using multiple delay devices to address a memory to access the delay value

Abstract

A pulse width measurement system is provided with components in an FPGA so that pulse widths can be measured that are smaller than the frequency limits of the FPGA system clock. For the measurement, an incoming pulse is fed into the FPGA to many (e.g. 32) I/O inputs in parallel. Each parallel input is then provided to a programmable delay device with each delay configured to a different ascending delay value. The input transition time is then detected by converting the outputs from the delay devices into data indicating the timing information. In one embodiment the outputs of the delay devices address data stored in BRAMs for later processing in the FPGA to determine the timing information.