The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Jun. 05, 2007
Filed:
Oct. 18, 2004
Tom Schram, Rixensart, BE;
Jacob Christopher Hooker, Leuven, BE;
Marcus Johannes Henricus Van Dal, Leuven, BE;
Tom Schram, Rixensart, BE;
Jacob Christopher Hooker, Leuven, BE;
Marcus Johannes Henricus van Dal, Leuven, BE;
Interuniversitair Microelektronica Centrum (IMEC), Leuven, BE;
Koninklijke Philips Electronics N.V., B.A. Eindhoven, NL;
Abstract
The invention relates to a method for fabricating a semiconductor device having a semiconductor body that comprises a first semiconductor structure having a dielectric layer and a first conductor, and a second semiconductor structure having a dielectric layer and a second conductor, that part of the first conductor which adjoins the dielectric layer having a work function different from the work function of the corresponding part of the second conductor. In one embodiment of the invention, after the dielectric layer has been applied to the semiconductor body, a metal layer is applied to the said dielectric layer, and then a silicon layer is deposited on the metal layer and is brought into reaction with the metal layer at the location of the first semiconductor structure, forming a metal silicide. In one embodiment, those parts of the conductors which have different work functions are formed by etching a layer other than the silicon layer, in particular a metal layer, at the location of one of the two semiconductor structures. Furthermore, a further metal layer is applied over the silicon layer and is used to form a further metal silicide at the location of the second transistor. One embodiment of the invention is particularly suitable for use in CMOS technology and results in both PMOS and NMOS transistors with favorable properties.