The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
May. 29, 2007
Filed:
Jun. 19, 2003
Robert John Bucki, Cary, NC (US);
Sang Hoo Dhong, Austin, TX (US);
Joel Abraham Silberman, Somers, NY (US);
Osamu Takahashi, Round Rock, TX (US);
Robert John Bucki, Cary, NC (US);
Sang Hoo Dhong, Austin, TX (US);
Joel Abraham Silberman, Somers, NY (US);
Osamu Takahashi, Round Rock, TX (US);
International Business Machines Corporation, Armonk, NY (US);
Abstract
A method of designing a logic circuit includes providing a leaf cell having at least one transistor. The leaf is suitable for use as a 1-cell or a 0-cell in the logic circuit. A first array of abutting leaf cells is tiled using at least one 1-cell and at least one 0-cell to define at least one logical expression by the relative positions of the array cells. Length optimized interconnects are added to the array. Each length optimized interconnect terminates at a last leaf cell in the array to which the interconnect makes contact. The leaf cell may be a floating leaf cell in which any pair of abutting cells are electrically isolated from one another until the length optimized interconnects are added to the design. The leaf cell array likely includes a set of rows and a set of columns in which the leaf cells in each row and the set of columns each correspond to an input of the logical expression.