The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
May. 29, 2007

Filed:

Mar. 12, 2003
Applicant:

Peter D. Capofreddi, San Francisco, CA (US);

Inventor:

Peter D. Capofreddi, San Francisco, CA (US);

Assignee:

HRL Laboratories, LLC, Malibu, CA (US);

Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
H04L 7/00 (2006.01); H03H 11/26 (2006.01); H04B 14/06 (2006.01);
U.S. Cl.
CPC ...
Abstract

A delta-sigma modulator that provides improved SNR performance in applications such as low-power mobile wireless communications and high frequency radar applications is disclosed. Multiple comparators, each comprising a sequence of three latches, connect the modulator's input filter circuitto the modulator's output interfaces, providing quantization of the integrated, filtered signal provided by the filter circuit. A clock signal having a cycle period Tenables a first latchconnected to the signal input of each comparatorto provide a digital signal to the signal input of a second latch. The second latchsupplies a digital signal to a third latchin the sequence, in response to the signal received from the first latch, by a lagged clock signal derived from the given clock signal Tby providing a first lag time Twhere T/2≧T>0. A third latch in the sequence is enabled by a clock signal having a second lag time T=T/2+T, and the delay T<<T/2. When T=T/2 the inverted clock signal supplied to the second latch is delayed and supplied to the third latch. When T=Tthe delayed clock signal supplied to the second latch is inverted and supplied to the third latch.


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