The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
May. 29, 2007
Filed:
Dec. 08, 2005
William Paul Hovis, Rochester, MN (US);
Alan James Leslie, Wappingers Falls, NY (US);
Phil Paone, Rochester, MN (US);
David W. Siljenberg, Byron, MN (US);
Salvatore Nicholas Storino, Rochester, MN (US);
Gregory John Uhlmann, Rochester, MN (US);
William Paul Hovis, Rochester, MN (US);
Alan James Leslie, Wappingers Falls, NY (US);
Phil Paone, Rochester, MN (US);
David W. Siljenberg, Byron, MN (US);
Salvatore Nicholas Storino, Rochester, MN (US);
Gregory John Uhlmann, Rochester, MN (US);
International Business Machines Corporation, Armonk, NY (US);
Abstract
An eFuse reference cell on a chip provides a reference voltage that is greater than a maximum voltage produced by an eFuse cell having an unblown eFuse on the chip but less than a minimum voltage produced by an eFuse cell having a blown eFuse on the chip. A reference current flows through a resistor and an unblown eFuse in the eFuse reference cell, producing the reference voltage. The reference voltage is used to create a mirrored copy of the reference current in the eFuse cell. The mirrored copy of the reference current flows through an eFuse in the eFuse cell. A comparator receives the reference voltage and the voltage produced by the eFuse cell. The comparator produces an output logic level responsive to the voltage produced by the eFuse cell compared to the reference voltage.