The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
May. 29, 2007

Filed:

Jul. 01, 2005
Applicants:

Kaoru Yamamoto, Yamato Kohriyama, JP;

Nobuhiko Ito, Tenri, JP;

Yoshimitsu Yamauchi, Nabari, JP;

Inventors:

Kaoru Yamamoto, Yamato Kohriyama, JP;

Nobuhiko Ito, Tenri, JP;

Yoshimitsu Yamauchi, Nabari, JP;

Assignee:
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G11C 11/34 (2006.01);
U.S. Cl.
CPC ...
Abstract

A semiconductor memory device having a virtual ground line type memory array structure includes a readout circuit for selecting a pair of selected bit lines connected to the source and the drain of a memory cell to be read, applying a predetermined voltage to between the paired selected bit lines, and sensing a memory cell current flowing through the memory cell to be read, and a counter potential generation circuit for generating from an intermediate node potential, which is higher than any level of the potential on the selected bit lines and supplied from an intermediate node on a current path for feeding the memory cell current in the readout circuit, a counter potential which varies in the same direction as of the intermediate node potential depending on the memory cell current so that its variation is greater than that of the intermediate node potential, wherein the counter potential is applied to an unselected bit line allocated next to one at a high level of the paired selected bit lines.


Find Patent Forward Citations

Loading…