The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
May. 29, 2007

Filed:

May. 11, 2005
Applicants:

Kazunari Kido, Kanagawa, JP;

Minoru Yamashita, Kanagawa, JP;

Kazuhiro Kurihara, Tokyo, JP;

Atsushi Hatakeyama, Tokyo, JP;

Hiroaki Wada, Tokyo, JP;

Inventors:

Kazunari Kido, Kanagawa, JP;

Minoru Yamashita, Kanagawa, JP;

Kazuhiro Kurihara, Tokyo, JP;

Atsushi Hatakeyama, Tokyo, JP;

Hiroaki Wada, Tokyo, JP;

Assignee:

Spansion LLC, Sunnyvale, CA (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G11C 11/34 (2006.01); G11C 16/04 (2006.01);
U.S. Cl.
CPC ...
Abstract

A semiconductor device includes a first memory cell array that includes memory cells for storing data and is managed on a sector basis, a second memory cell array including memory cells storing sector protection information on the sector basis, and a control circuit checking the sector protection information stored in the second memory cell array whenever the sector to be programmed or erased is selected. Thus, the sector protection information in all the sectors does not have to be latched at the time of power on. The latch circuit equal in number to the sector does not have to be provided. It is thus possible to reduce the number of the circuits drastically and the chip area can be reduced.


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