The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
May. 29, 2007
Filed:
Jul. 19, 2005
Derick G. Behrends, Rochester, MN (US);
Chad A. Adams, Rochester, MN (US);
Ryan C. Kivimagi, Rochester, MN (US);
Anthony G. Aipperspach, Rochester, MN (US);
Robert N. Krentler, Austin, TX (US);
Derick G. Behrends, Rochester, MN (US);
Chad A. Adams, Rochester, MN (US);
Ryan C. Kivimagi, Rochester, MN (US);
Anthony G. Aipperspach, Rochester, MN (US);
Robert N. Krentler, Austin, TX (US);
International Business Machines, Armonk, NY (US);
Abstract
A glitch protect valid cell and method for maintaining a desired logic state value. The glitch protect valid cell includes a memory element, a state machine, and a glitch protect circuit. The glitch protect circuit includes a propagation delay assembly coupled to a restore assembly. The propagation delay assembly includes a first pull down network coupled to a NOR gate. The restore assembly includes a second pull down network coupled to the propagation delay assembly. Responsive to a glitch signal and timing signal, the first pull down network resets the initial state value of a true valid bit to ultimately enable a pull up network in the NOR gate. Responsive to enablement of the NOR gate pull up network, the second pull down network resets the complement valid bit in the memory element to consequently restore the initial state of the true valid bit.