Apparatus and fabrication methods for incorporating sub-millimeter, high-resistivity mechanical components with low-resistivity conductors while maintaining electrical isolation therebetween

Abstract

Fabricating electrical isolation properties into a MEMS device is described. One embodiment comprises a main substrate layer of a high-resistivity semiconductor material, such as high-resistivity silicon. The high-resistivity substrate is then controllably doped to provide a region of high-conductivity in the main substrate. Electrical isolation is achieved in such an embodiment by patterning the high-conductivity region either by masking the main substrate during the doping or etching through the doped, high-conductivity region in order to form regions of high conductivity. Effective isolation results from confinement of electrical currents to the lowest-resistance path. An alternative embodiment employs the fabrication of pn junctions and the use of reverse biasing to enhance the electrical isolation. A further embodiment comprises a main substrate layer of low-resistivity semiconductor material with a layer of insulator deposited thereon. High-conductivity or low-resistivity material is then grown on top of the insulator to create electrically isolated conductors.