The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Patent No.:

US 7222320 B1

PDF
Full Text
Expired
Date of Patent:
May. 22, 2007

Filed:

Dec. 29, 2004
Applicant:

Yasushige Ogawa, Kasugai, JP;

Inventor:

Yasushige Ogawa, Kasugai, JP;

Assignee:

Fujitsu Limited, Kawasaki, JP;

Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
G06F 17/50 (2006.01);
U.S. Cl.
CPC ...
Abstract

A layout method of decoupling capacitors while ensuring the decoupling capacitance necessary for each grid area. The method includes calculating the total power consumption of logic cells, arranging the decoupling capacitance throughout the subject area in correspondence with the total power consumption, dividing the subject area into a plurality of grid areas, arranging the logic cells in each grid area, determining whether the decoupling capacitance is sufficient in each grid area for the logic cells in that grid area, and performing a supplementing process of the decoupling capacitance based on whether the decoupling capacitance is sufficient.


Find Patent Forward Citations

Ogawa, Yasushige. (2007). Layout method of decoupling capacitors (U.S. Patent No. 7222320). U.S. Patent and Trademark Office. https://idiyas.com/patent/badge/7222320

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