The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
May. 22, 2007
Filed:
Apr. 23, 2002
Shinji Kashiwagi, Tokyo, JP;
Shinji Kashiwagi, Tokyo, JP;
NEC Electronics Corporation, Kanagawa, JP;
Abstract
A scan test circuit () including a path for capturing a control signal during a test mode is disclosed. Scan test circuit () may include a control supply circuit (), a clock control circuit (), a control signal test circuit (), and a scan flip-flop (). Control supply circuit () may receive a control signal (Enable signal), which may be used for enabling a clock signal (CLK) in a gated clock system. A control supply test circuit () may provide a signal path that can apply control signal (Enable signal) to scan flip-flop () for capturing. In this way, functionality of a combination circuit used for generating a control signal (Enable signal) may be verified.