The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
May. 22, 2007
Filed:
Feb. 05, 2003
Sagheer Ahmad, Sunnyvale, CA (US);
Erik Norden, Santa Clara, CA (US);
Rob Ober, San Jose, CA (US);
Infineon Technologies AG, Munich, DE;
Abstract
An idle mode system has a clock gating circuit, a bus interface unit, memory interfaces and an interrupt and idle control unit. The clock gating circuit receives a first clock and designated idle-acknowledge signals. The clock gating circuit produces a second clock signal based on the first clock signal when fewer than all designated idle-acknowledge signals are received. The clock gating circuit produces no second clock signal when all designated idle-acknowledge signals are received. The bus interface unit receives bus access requests and receives the first and second clock signals. When a bus access request is made, the bus interface unit de-asserts its idle-acknowledge signal and passes the bus access request. The memory interfaces operate on the second clock. One interface receives the bus access request from the bus interface unit, withdraws its idle-acknowledge signal, processes the bus access request, and re-asserts its idle-acknowledge signal upon completion.