The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
May. 22, 2007

Filed:

Dec. 27, 2002
Applicants:

Yoshihiro Asaka, Kanagawa, JP;

Hidetoshi Sakaki, Kanagawa, JP;

Noboru Furuumi, Tokyo, JP;

Masami Maeda, Kanagawa, JP;

Masaru Tsukada, Kanagawa, JP;

Junichi Muto, Kanagawa, JP;

Misako Tamura, Shizuoka, JP;

Inventors:

Yoshihiro Asaka, Kanagawa, JP;

Hidetoshi Sakaki, Kanagawa, JP;

Noboru Furuumi, Tokyo, JP;

Masami Maeda, Kanagawa, JP;

Masaru Tsukada, Kanagawa, JP;

Junichi Muto, Kanagawa, JP;

Misako Tamura, Shizuoka, JP;

Assignee:

Hitachi, Ltd., Tokyo, JP;

Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
G06F 15/173 (2006.01);
U.S. Cl.
CPC ...
Abstract

A storage system comprising a host device, a storage device, a switching device, and a management terminal is provided. The host device has a plurality of first logical blocks. The storage device has a plurality of second logical blocks. The switching device transfers data between the host device and the storage device through a plurality of paths. The management terminal receives information on the first logical blocks from the host device, receives information on the second logical blocks from the storage device, and generates information showing connecting paths between the first logical blocks and the second logical blocks based on the information on the first logical blocks received and the information on the second logical blocks received. Accordingly, it is possible to get hold of the connected configuration of the first logical blocks and the second logical blocks.


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