The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
May. 22, 2007
Filed:
Nov. 14, 2005
Francois Jacquet, Froges, FR;
Florent Vautrin, Vizille, FR;
Francois Jacquet, Froges, FR;
Florent Vautrin, Vizille, FR;
ST Microelectronics SA, Montrouge, FR;
Abstract
A memory circuit includes a plurality of storage cells () arranged in rows and columns thus forming a storage matrix. The storage cells () corresponding to the same bit line (-) are divided into several groups (-) of cells for the same column, these groups having their own biasing circuit () in order to act on the difference between the logic level low voltage and the substrate voltage of the link transistors. When a storage cell is not selected, the biasing circuit makes the voltage between source/drain and substrate equal to a negative voltage in order to minimize the leakage current. During a read operation, the substrate voltage and the source/drain voltage are brought back to the same level such that a maximum current will flow when the link transistor is conducting.