The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
May. 22, 2007

Filed:

Jul. 29, 2004
Applicants:

Brijesh Tripathi, Santa Clara, CA (US);

Wayne Douglas Young, Milpitas, CA (US);

Adam E. Levinthal, Redwood City, CA (US);

Stephen M. Ryan, Cupertino, CA (US);

Inventors:

Brijesh Tripathi, Santa Clara, CA (US);

Wayne Douglas Young, Milpitas, CA (US);

Adam E. Levinthal, Redwood City, CA (US);

Stephen M. Ryan, Cupertino, CA (US);

Assignee:

Nvidia Corporation, Santa Clara, CA (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G06F 15/00 (2006.01); G06F 13/00 (2006.01); G09G 5/36 (2006.01); G06T 1/20 (2006.01); G06T 1/00 (2006.01); G06T 15/00 (2006.01); G06F 15/167 (2006.01); G06F 13/28 (2006.01);
U.S. Cl.
CPC ...
Abstract

Apparatus, system, and method for delivering data to multiple memory clients are described. In one embodiment, a graphics processing apparatus includes an output pipeline including a set of memory clients. The graphics processing apparatus also includes a memory controller connected to the output pipeline. The memory controller is configured to retrieve data requested by respective ones of the set of memory clients from a memory. The graphics processing apparatus further includes a buffering module connected between the memory controller and the output pipeline. The buffering module includes a unitary buffer and a buffer controller connected to the unitary buffer. The buffer controller is configured to coordinate storage of the data in the unitary buffer, and the buffer controller is configured to coordinate delivery of the data from the unitary buffer to respective ones of the set of memory clients.


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