The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
May. 22, 2007

Filed:

Sep. 29, 2004
Applicants:

Mark Adam Bachman, Sinking Spring, PA (US);

Daniel Patrick Chesire, Winter Garden, FL (US);

Taeho Kook, Orlando, FL (US);

Sailesh M. Merchant, Macungie, PA (US);

Inventors:

Mark Adam Bachman, Sinking Spring, PA (US);

Daniel Patrick Chesire, Winter Garden, FL (US);

Taeho Kook, Orlando, FL (US);

Sailesh M. Merchant, Macungie, PA (US);

Assignee:

Agere Systems, Inc., Allentown, PA (US);

Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
G01R 31/02 (2006.01);
U.S. Cl.
CPC ...
Abstract

An interface assembly () and method for testing a semiconductor wafer prior to performing a flip chip bumping process are provided. The interface assembly includes a flip chip bonding pad () having a region () for performing the bumping process. A test pad () is integrally constructed with the bonding pad and includes a probe region () for performing wafer-level testing prior to performing the bumping process. The integral construction of the bonding and testing pads avoids, for example, an introduction of propagation delays to test signals passing therethrough, thereby improving the accuracy and reliability of wafer test results.


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