The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
May. 15, 2007
Filed:
Apr. 30, 2004
Stefan R. Bohult, Phoenix, AZ (US);
Stefan R. Bohult, Phoenix, AZ (US);
Bull HN Information Systems Inc., Billerica, MA (US);
Abstract
A simple and accurate processor derating method includes: sampling a real-time counter/clock too obtain an initial time value T; resetting an Icnt Counter; incrementing the Icnt Counter to reflect the processing of each instruction; comparing the count in the Icnt Counter to a predetermined count IcntMax and if the count in the Icnt Counter is at least IcntMax, then sampling the RTC to obtain a second time T. Tis then subtracted from Tto obtain a time difference DT which is multiplied by ((1−1/DF)−1) to obtain a Degradation Delay DD period, DF being a constant having a value which is the desired submodel performance with respect to full performance. The Degradation Delay is instituted, the RTC is sampled from time to time to obtain a test third time T. When a test Tminus Tis not less than DD, then Tis set to T. Then, the procedure is repeated for a next group of instructions. Optionally, further accuracy can be achieved by treating 'wait-type' and/or 'RTC-access-type' instructions specially and also by calculating a DDExtra period value which is used to adjust the next DD.