The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
May. 15, 2007

Filed:

Sep. 17, 2004
Applicant:

Karen Pamelia Shrier, Jarrell, TX (US);

Inventor:

Karen Pamelia Shrier, Jarrell, TX (US);

Assignee:

Electronic Polymers, Inc., Round Rock, TX (US);

Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
H02H 9/00 (2006.01);
U.S. Cl.
CPC ...
Abstract

A device () for suppressing electrostatic discharge comprises first and second multilayer structures () surrounding an electrostatic discharge reactance layer (), the resistance of said electrostatic discharge reactance layer () varying in response to the occurrence of an electrostatic discharge signal. Each multilayer structure () comprises a barrier layer (), a terminal layer () and an electrode layer (). Alternatively, a conductive layer () can be used instead of a second multilayer structure (). An ESD suppression device () can be embedded in a printed circuit board () providing a way to protect board components from harmful ESD events.


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