The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
May. 15, 2007
Filed:
Apr. 30, 2004
Vasisht Mantra Vadi, San Jose, CA (US);
David P. Schultz, San Jose, CA (US);
John D. Logue, Placerville, CA (US);
John Mcgrath, Cork, IE;
Anthony Collins, Dublin, IE;
F. Erich Goetting, Cupertino, CA (US);
Vasisht Mantra Vadi, San Jose, CA (US);
David P. Schultz, San Jose, CA (US);
John D. Logue, Placerville, CA (US);
John McGrath, Cork, IE;
Anthony Collins, Dublin, IE;
F. Erich Goetting, Cupertino, CA (US);
Xilinx, Inc., San Jose, CA (US);
Abstract
Method and apparatus for dynamic configuration of function block logic of an integrated circuit is described. The integrated circuit includes a reconfiguration port coupled to a controller. The controller is coupled to an array of memory cell. A portion of the array of memory cells is coupled for read/write communication with the controller, and another portion of the array of memory cells is not coupled for read/write communication with the controller. The portion of the array of memory cells is configurable at an operational frequency of the integrated circuit for dynamic reconfiguration of the function block logic of the integrated circuit.