The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
May. 15, 2007
Filed:
Feb. 02, 2005
David M. Lewis, Toronto, CA;
Paul Leventis, Toronto, CA;
Andy L. Lee, San Jose, CA (US);
Henry Kim, San Jose, CA (US);
Bruce Pedersen, Sunnyvale, CA (US);
Chris Wysocki, Toronto, CA;
Christopher F. Lane, San Jose, CA (US);
Alexander Marquardt, Toronto, CA;
Vikram Santurkar, Fremont, CA (US);
Vaughn Timothy Betz, Toronto, CA;
David M. Lewis, Toronto, CA;
Paul Leventis, Toronto, CA;
Andy L. Lee, San Jose, CA (US);
Henry Kim, San Jose, CA (US);
Bruce Pedersen, Sunnyvale, CA (US);
Chris Wysocki, Toronto, CA;
Christopher F. Lane, San Jose, CA (US);
Alexander Marquardt, Toronto, CA;
Vikram Santurkar, Fremont, CA (US);
Vaughn Timothy Betz, Toronto, CA;
Altera Corporation, San Jose, CA (US);
Abstract
An embodiment of this invention pertains to a versatile and flexible logic element and logic array block ('LAB'). Each logic element includes a programmable combinational logic function block such as a lookup table ('LUT') and a flip-flop. Within the logic element, multiplexers are provided to allow the flip-flop and the LUT to be programmably connected such that either the output of the LUT may be connected to the input of the flip-flop or the output of the flip-flop may be connected to the input of the LUT. An additional multiplexer allows the output of the flip-flop in one logic element to be connected to the input of a flip-flop in a different logic element within the same LAB. Output multiplexers selects between the output of the LUT and the output of the flip-flop to generate signals that drive routing lines within the LAB and to routing lines external to the LAB. These output multiplexers are constructed such that the combinational output (output from the LUT) is faster than the output from the flip-flop. A collection of routing lines and multiplexers within the LAB are used to provide inputs to the LUTs. Each of the input multiplexers for each logic element is connected to a subset of the routing lines within the LAB using a specific pattern of connectivity of multiplexers to associated wires that maximizes the efficiency of use of the routing wires. Control signals for the set of logic elements within the LAB are generated using a secondary signal generation unit that minimizes contention for shared signals. One of the control signals is an “add-or-subtract control signal” that allows all of the LEs in a LAB to perform either addition or subtraction under the control of a logic signal. In a PLD supporting redundancy, the carry chain for the LABs is arranged in the same direction that redundancy shifts to remap defective LABs and a multiplexer on the carry input of a LAB is used to select the appropriate carry output from another LAB depending on whether redundancy is engaged.