The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
May. 15, 2007

Filed:

Dec. 04, 2003
Applicants:

Gopakumar Parameswaran, Santa Clara, CA (US);

Cuong C. Ly, Newark, CA (US);

Douglas L. Yanagawa, Los Altos, CA (US);

Mark N. Yamashita, San Jose, CA (US);

Yuval Bachar, Sunnyvale, CA (US);

Inventors:

Gopakumar Parameswaran, Santa Clara, CA (US);

Cuong C. Ly, Newark, CA (US);

Douglas L. Yanagawa, Los Altos, CA (US);

Mark N. Yamashita, San Jose, CA (US);

Yuval Bachar, Sunnyvale, CA (US);

Assignee:

Cisco Technology, Inc., San Jose, CA (US);

Attorneys:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
H01R 12/04 (2006.01); H05K 1/11 (2006.01);
U.S. Cl.
CPC ...
Abstract

Two pairs of vias are arranged in a printed circuit board. A first pair of vias, which conveys a first signal pair, is arranged in a plane that is substantially equidistant from the vias in a second pair of vias, which conveys a second signal pair. Similarly, the second pair of vias is located in a plane that is substantially equidistant from each via in the first pair of vias. In some embodiments, such an arrangement reduces the crosstalk effect of the first signal pair on the second signal pair and vice versa.


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