The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
May. 08, 2007
Filed:
Nov. 06, 2003
Wendy A. Belluomini, Austin, TX (US);
Ramyanshu Datta, Austin, TX (US);
Jente Benedict Kuang, Austin, TX (US);
Chandler T. Mcdowell, Austin, TX (US);
Robert K. Montoye, Austin, TX (US);
Hung C. Ngo, Austin, TX (US);
Wendy A. Belluomini, Austin, TX (US);
Ramyanshu Datta, Austin, TX (US);
Jente Benedict Kuang, Austin, TX (US);
Chandler T. McDowell, Austin, TX (US);
Robert K. Montoye, Austin, TX (US);
Hung C. Ngo, Austin, TX (US);
International Business Machines Corporaiton, Armonk, NY (US);
Abstract
A 4-to-2 carry save adder with a reduction in the delay of outputting the sum and carry bits. The 4-to-2 carry save adder may include a lower order full order coupled to a higher order full adder. The carry save adder may further include a logic unit coupled to the higher order full adder where the logic unit is configured to generate a carry bit to be inputted to the higher order full adder that normally would be generated from the carry save adder located in the previous stage. By generating this carry bit (carry-in bit) in the current stage and not in the previous stage, the delay of the carry-in bit inputted to the higher order full adder is reduced thereby reducing the delay of outputting the sum and carry bits by the higher order full adder.