Multi-layered memory cell structure

Abstract

A high-density memory device and design method that utilizes some or all of the existing stacked process conductor layers provided by a manufacturing process to enhance the number of available bitlines and/or wordlines within the memory device. The memory device includes a plurality of memory cells arranged in columns and rows, a plurality of wordlines, a plurality of bitlines, at least one via-stack, wherein said existing stacked process conductor layers are used to implement at least one additional wordline or bitline. The via-stacks consist of a plurality of vias, are located close to a memory cell, and adapted to electrically connect the memory cell to multiple bitlines or multiple wordlines or both0. This design method increases the number of possible connections to or from each individual memory cell. When this design method is combined with varied configurations of basic underlying ROM cell types, even further increased cell density can be achieved.