The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
May. 08, 2007
Filed:
Jul. 21, 2005
Derick Gardner Behrends, Rochester, MN (US);
Ryan Charles Kivimagi, Chatfield, MN (US);
Chihhung Liao, Fremont, CA (US);
Derick Gardner Behrends, Rochester, MN (US);
Ryan Charles Kivimagi, Chatfield, MN (US);
Chihhung Liao, Fremont, CA (US);
International Business Machines Corporation, Armonk, NY (US);
Abstract
An apparatus and method provide logically controlled masking of one or more maskable data bits from a plurality of data bits that are input to a dynamic logic circuit. No masking logic and attendant delay penalty is coupled in the data path that is not needed for unmasked bits from the plurality of data bits that do not need masking. A system clock has a precharge phase and an evaluate phase. A first clock buffer is coupled to a precharge switch and precharges a dynamic node during the precharge phase. A second clock buffer having substantially the same delay from system clock input to an output of the second clock buffer is gated by a derivative of a mask. The output of the second clock buffer controls one or more switches in series with switches controlled by the maskable data bits.