The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
May. 08, 2007

Filed:

May. 30, 2003
Applicants:

Rahul Saini, Union City, CA (US);

Andy Lee, San Jose, CA (US);

Ninh Ngo, San Jose, CA (US);

Inventors:

Rahul Saini, Union City, CA (US);

Andy Lee, San Jose, CA (US);

Ninh Ngo, San Jose, CA (US);

Assignee:

Altera Corporation, San Jose, CA (US);

Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
H03K 19/177 (2006.01);
U.S. Cl.
CPC ...
Abstract

An embodiment of the present invention provides a programmable logic device ('PLD') including one or more dedicated blocks of circuitry within one or more repairable logic array regions. Aspects of the present invention provide circuitry and methods for controlling shifting of programming data in normal and redundant modes for both dedicated block regions and fully repairable logic array regions during both regular and test programming sequences of a PLD. Other aspects provide circuitry and methods for interface routing between dedicated blocks and repairable logic array regions in both normal and redundant modes. Various other aspects are also disclosed.


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