The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
May. 08, 2007
Filed:
May. 16, 2005
Sheng Teng Hsu, Camas, WA (US);
Tingkai LI, Vancouver, WA (US);
David R. Evans, Beaverton, OR (US);
Wei-wei Zhuang, Vancouver, WA (US);
Wei Pan, Vancouver, WA (US);
Sheng Teng Hsu, Camas, WA (US);
Tingkai Li, Vancouver, WA (US);
David R. Evans, Beaverton, OR (US);
Wei-Wei Zhuang, Vancouver, WA (US);
Wei Pan, Vancouver, WA (US);
Sharp Laboratories of America, Inc., Camas, WA (US);
Abstract
Asymmetrically structured memory cells and a fabrication method are provided. The method comprises: forming a bottom electrode; forming an electrical pulse various resistance (EPVR) first layer having a polycrystalline structure over the bottom electrode; forming an EPVR second layer adjacent the first layer, with a nano-crystalline or amorphous structure; and, forming a top electrode overlying the first and second EPVR layers. EPVR materials include CMR, high temperature super conductor (HTSC), or perovskite metal oxide materials. In one aspect, the EPVR first layer is deposited with a metalorganic spin coat (MOD) process at a temperature in the range between 550 and 700 degrees C. The EPVR second layer is formed at a temperature less than, or equal to the deposition temperature of the first layer. After a step of removing solvents, the MOD deposited EPVR second layer is formed at a temperature less than, or equal to the 550 degrees C.