Self-aligned 2-bit 'double poly cmp' flash memory cell

Abstract

Fabrication of a memory cell, the cell including a first floating gate stack (A), a second floating gate stack (B) and an intermediate access gate (AG), the floating gate stacks (A, B) including a first gate oxide (), a floating gate (FG), a control gate (CG; CGl, CGu), an interpoly dielectric layer (), a capping layer () and side-wall spacers (), the cell further including source and drain contacts (), wherein the fabrication includes: defining the floating gate stacks in the same processing steps to have equal heights; depositing over the floating gate stacks a poly-Si layer () with a larger thickness than the floating gate stacks' height; planarizing the poly-Si layer (); defining the intermediate access gate (AG) in the planarized poly-Si layer () by means of an access gate masking step over the poly-Si layer between the floating gate stacks and a poly-Si etching step.