The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Patent No.:

US 7213187 B1

PDF
Full Text
Expired
Date of Patent:
May. 01, 2007

Filed:

Jan. 19, 2005
Applicant:

Chih-wen Lin, Kao-Hsiung, TW;

Inventor:

Chih-Wen Lin, Kao-Hsiung, TW;

Assignee:

Faraday Technology Corp., Hsin-Chu, TW;

Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
G01R 31/28 (2006.01);
U.S. Cl.
CPC ...
Abstract

A digital logic test method for systematically testing a pipeline-structured integrated circuit chip is disclosed. The method includes the steps of: providing an integrated circuit chip capable of executing a plurality of instructions during a period of time, each of the instructions being executed according to a plurality of sequentially ordered operation segments, sorting the instructions, and designing a plurality of test patterns to test the integrated circuit according to the sorting result and STAGE test segments corresponding to the STAGE operation segments.


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Lin, Chih-Wen. (2007). Digital logic test method to systematically approach functional coverage completely and related apparatus and system (U.S. Patent No. 7213187). U.S. Patent and Trademark Office. https://idiyas.com/patent/badge/7213187

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